1. Field of the Invention
This invention relates to the field of semiconductor circuits and more specifically, to the composition of metal layers used in the interconnection of various devices in an integrated circuit.
2. Prior Art
Large scale integrated semiconductor circuits have multiple layers of conducting films interconnecting the various devices located on a semiconductor substrate. Modern devices typically have at least three metal layers; the first level of metalization (metal 1) provides for local interconnects while the latter metalization layers (metal 2 or metal 3, etc.) provide for longer interconnects, (i.e. across the entire chip). The conducting layers are normally separated by intermetal dielectric layers such as SiO.sub.2 which act to isolate the potential of the conducting layers. Sometimes it is desired to interconnect the lines of different layers. When this is the case, a hole is etched through the intermetal dielectric so that when the upper metal layer (metal 2 or 3 or 4) is deposited it can form a contact with the lower level metal (metal 1 or 2 or 3) at the desired location. Such holes formed in dielectric layers are commonly referred to as via holes. Processes for etching via holes are well-known in the art.
A typical prior art method of forming an intermetal via hole is shown in FIG. 1. A thin single layer of aluminum or an aluminum alloy 11 is typically used as the conducting material (metal 1) to interconnect the device structures formed on a silicon substrate. An intermetal dielectric 13 is used to isolate the single aluminum layer 11 from a later formed conducting layer (metal 2). When it is desired to interconnect the two metal layers (metal 1 and metal 2) a via hole 19 is etched through the intermetal dielectric layer 13 to the aluminum layer 11. A photoresist layer 17 is masked, exposed and developed with well know lithography processes to form a mask which defines the area where the via is to be etched. The intermetal dielectric layer 13 is etched with commonly known etching techniques such as wet etching plasma etching or reactive ion etching. A wide variety of gas mixtures or chemicals can be employed as the active ingredient for the etch. Once the inner dielectric layer has been completely etched through, the underlying aluminum layer is exposed. The aluminum layer can react with fluorine atoms to form AlF.sub.3. When the semiconductor device is removed from the reaction chamber the aluminum layer readily reacts with oxygen in the atmosphere to form Al.sub.2 O.sub.3. Al.sub.2 O.sub.3 and AlF.sub.3 both form along the aluminum surface 20 in the via hole. Al.sub.2 O.sub.3 and AlF.sub. 3 are both insulating materials and are both very difficult to remove.
After removing the photoresist layer 17, an outer layer of conducting film (metal 2) is formed on the dielectric layer and on the underlying aluminum layer in the via hole. The conducting film, however, actually forms on top of the undesired Al.sub.2 O.sub.3 and AlF.sub.3, which significantly increases the contact resistance of the device. Such an increase in contact resistance degrades the integrated circuit's performance.
What is desired, therefore, is a novel coating for an aluminum layer which will prevent the formation of Al.sub.2 O.sub.3 and AlF.sub.3 during the etching of a via hole.